(a) Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device and, more particularly, to a method for manufacturing an electrically erasable programmable read only memory (EEPROM).
(b) Description of the Related Art
Nonvolatile semiconductor memory devices retain data written thereto even when their power is turned off. Active research has been conducted to develop nonvolatile semiconductor memory devices.
Of nonvolatile semiconductor memory devices, EEPROMs or flash memories have a memory ceil structure advantageous for finer patterning, and consequently are stilted for implementing highly integrated devices. Japanese Patent After-Exam. (KOKOKU) Publication No. 63-41224 discloses a technique for forming source regions in a self aligned structure in which gate electrode layers are used as a mask to obtain memory cells having a finer pattern. FIG. 1 is a schematic plan view showing a memory device having self aligned sources disclosed in the publication as mentioned above. FIGS. 2A, 2B and 2C, FIGS. 3A, 3B and 3C, 4A, Figs. 4B and 4C, 5A, FIGS. 5B and 5C, 6A, FIGS. 6B and 6C, and FIGS. 7A, 7B and 7C are cross-sectional views of the semiconductor memory device of FIG. 1 for showing consecutive steps of a manufacturing process of the prior art. FIGS. 2A-7A show cross-sections taken along line A--A' in FIG. 1, FIGS. 2B-7B show cross-sections taken along line B--B' and FIGS. 2C-7C show cross-sections taken along line C--C' in FIG. 1.
First, as shown in FIGS. 2A, 2B and 2C (hereinafter also referred to as FIGS. 2A-2C), first insulating films or field oxide films 2 each having a thickness of 3000-8000 angstroms are formed on a P-type silicon substrate 1 by using a known LOCOS technique, the field oxide films extending in a first direction (horizontal direction as viewed in FIG. 1) and in parallel to each other. Subsequently, as shown in FIGS. 3A-3C, second insulating films or first gate insulating films 4, each made of a thermal oxide film having a thickness of 100-200 angstroms, are formed between two of the field oxide films, following which a first polysilicon layer having a thickness of 1000-3000 angstroms is formed on the entire surface by chemical vapor deposition (CVD). Then, patterning is performed on the first polysilicon layer to form floating gate layers 3 each extending in the first direction on the first gate insulating film 4 and the edge portions of the field oxide films 2 (FIGS. 3A-3C).
Then a third insulating film is formed on the entire surface as an ONO-laminate having a thickness of 100-300 angstroms and three layers including a silicon oxide film, a silicon nitride film, and another silicon oxide film. Next, a second polysilicon layer having a thickness of 2000-4000 angstroms is formed by CVD on the entire surface. Then, by using a known anisotropic etching technique, patterning is performed on the second polysilicon layer to make control gates 5 extending in a second direction perpendicular to the first direction. Patterning is also performed on the second gate insulating film 6 and floating gate layers 3 using each of the control gates 5 as a mask to obtain gate structures as shown in FIGS. 4A-4C.
Subsequently, a photoresist pattern 7 is formed, in which openings 13 thereof have edges on the central portions of the control gates 5, as shown in FIGS. 5A-5C. With the photoresist pattern 7 and the control gates 5 used as a mask, anisotropic etching is performed on the field oxide films 2 to selectively expose portions of the semiconductor substrate 1 in which source regions are to be formed. Then, by using an ion implantation technique, N-type impurity ions such as phosphorus (P) ions are implanted to the exposed portions of the semiconductor substrate 1 to form source regions extending in the second direction, i.e. vertical direction as viewed in FIG. 1. After removing the photoresist pattern 7 by an ion-etching technique or the like, N-type impurity ions such as arsenic (As) ions are selectively introduced to the substrate regions including the source regions 8b and other portions opposite to the source regions 8b with respect to the gate structures, thereby obtaining N-type source regions 8b and N-type drain regions 8a, as shown in FIGS. 6A-6C. The source regions 8b extend in the vertical direction as viewed in FIG. 1 while the drain regions 8a are separated from each other by the field oxide films 2 in the vertical direction as viewed in FIG. 1.
Next, as shown in FIGS. 7A-7C, after depositing an interlayer insulating film 11 made of a silicon oxide film containing, for example, boron (B) or phosphorus (P), contact holes 10 are formed in the interlayer insulating films 11 and the first gate insulating film 4 for exposing portions of the drain regions 8a by using a known photolithographic technique. Then, an aluminum layer is deposited on the entire surface, and patterning is performed thereon to obtain aluminum interconnection 9.
The conventional method for manufacturing a nonvolatile semiconductor memory device as described above is employed primarily for manufacturing flash memories in which erasing of data is performed from the source regions by applying a high voltage, e.g. 12 volts, to the source regions. Since the method allows source regions to be formed in a self aligned structure, it is not necessary to provide an alignment margin between the source regions and the gate electrode layers. Accordingly, the conventional method is suited for a finer patterning of memory cells in flash memories.
It has been long requested that nonvolatile semiconductor memory devices have more reliable characteristics and be manufactured in a higher integration and in a higher yield.